Well-structure anti-punch-through microwire device

ABSTRACT

A well-structure anti-punch-through microwire device and associated fabrication method are provided. The method initially forms a microwire with alternating highly and lightly doped cylindrical regions. A channel ring is formed external to the microwire outer shell and surrounding a first dopant well-structure region in the microwire, between source and drain (S/D) regions of the microwire. The S/D regions are doped with a second dopant, opposite to the first dopant. A gate dielectric ring is formed surrounding the channel ring, and a gate electrode ring is formed surrounding the gate dielectric ring. The well-structure, in contrast to conventional micro or nanowire transistors, helps prevent the punch-through phenomena.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention generally relates to integrated circuit (IC) fabricationand, more particularly, to a well-structure microwire transistor device.

2. Description of the Related Art

As-grown, in-situ end-doped core-shell-shell (ECSS) nanowires are knownfor use in the fabrication of transistor devices. However, there areseveral problems associated with these wires, such as the ability tocontrol the dopant concentration and width of the intrinsic channel,poor wire diameter and length uniformity, and harvesting of thenanowires (NWs) for dispersion onto a larger substrate.

The NW wire diameter can affect the depth of the depletion layer withinthe transistor channel, and poor uniformity can cause some wires to befully depleted, with adjacent wires only partially depleted. This isespecially problematic for the control of threshold voltagedistribution.

It would be advantageous if the performance of NW transistor devicescould be made more uniform.

SUMMARY OF THE INVENTION

A microwire architecture is disclosed herein that permits the use oflarger diameter wires having a fully-doped, modulated P-N-P, or N-P-Nstructure with an intrinsic epitaxial Si shell for NMOS or PMOStransistor applications. The use of larger diameters (d_(wire)>500 nm)is desirable for a number of reasons. First, growth conditions are morefavorable for larger diameter wires—providing a higher yield and greateruniformity. The use of an epitaxial intrinsic Si layer permits a finercontrol of the depletion region, so the devices can become fullydepleted, enabling better control of the device parameters (e.g.,threshold voltage) and uniformity. The modulated doping transientlengths (i.e., the growth length between when the source/drain dopant ison and off) have less impact on the overall device performance. The useof an epitaxial Si layer for the channel also permits precise thresholdvoltage adjustments to be made independent of the modulated growthprocess.

Further, the effective channel width scales with the diameter, so that a1 μm microwire has a channel width 10 times that of conventionalnanowires with a typical diameter of approximately 100 nanometers (nm).Larger channel widths permit higher I_(on) per wire and reduce the needfor multiple wires to be deposited per device.

Accordingly, a method is provided for fabricating a well-structureanti-punch-through microwire device. The method initially forms amicrowire with alternating highly and lightly doped cylindrical regions.A channel ring is formed surrounding a first dopant well-structureregion in the microwire, between source and drain (S/D) regions of themicrowire. The S/D regions are doped with a second dopant, opposite tothe first dopant. A gate dielectric ring is formed surrounding thechannel ring, and a gate electrode ring is formed surrounding the gatedielectric ring. The well-structure, in contrast to conventional microor nanowire transistors, helps prevent the punch-through phenomena. Inone aspect, the channel ring is formed external to the microwire outershell wall.

The microwire is formed by depositing a nucleation catalyst on asubstrate. A silane precursor and the first dopant are introduced. Asthe microwire is grown, the introduction of the second dopant is pulsemodulated. In another aspect, the introduction of both the first andsecond dopant is pulse modulated. For example, when the first dopant isintroduced, the flow of the second dopant is stopped, and when thesecond dopant is introduced, the flow of the first dopant isinterrupted. After removing the catalyst, an intrinsic Si layer isepitaxially grown surrounding the microwire, which may be used to formthe channel ring. The intrinsic Si is oxidized to form the gatedielectric ring surrounding the channel ring. Then, a gate electrodematerial is deposited overlying the oxidized intrinsic Si, and the gateelectrode material, oxidized intrinsic Si, and intrinsic Si layersurrounding the source and drain regions are selectively etched away.

Additional details of the above-described method and well-structureanti-punch-through microwire device are presented below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are partial cross-sectional views of a well-structureanti-punch-through microwire device.

FIGS. 2A and 2B are partial cross-sectional views of a first variationof the well-structure anti-punch-through microwire device of FIGS. 1Aand 1B.

FIGS. 3 through 5 are partial cross-sectional views depicting steps inthe fabrication of a completed well-structure microwire device.

FIG. 6 is a diagram depicting a silicon microwire growth process using avapor-liquid-solid (VLS) approach.

FIG. 7 is a diagram depicting a VLS Si microwire growth process using analternate doping technique.

FIG. 8 depicts a conventional IC-based CMOS device on a bulk Sisubstrate (prior art).

FIG. 9 depicts steps in the fabrication of an in-situ-doped microwirestructure with shell layers of intrinsic Si, oxide, and conductive gate,based on a VLS-type growth process.

FIG. 10 is a flowchart illustrating a method for the fabrication of awell-structure anti-punch-through microwire device.

DETAILED DESCRIPTION

FIGS. 1A and 1B are partial cross-sectional views of a well-structureanti-punch-through microwire device. The device 100 comprises amicrowire 102 with alternating highly and lightly doped cylindricalregions, including a first dopant well-structure region 104. A channelring 106 surrounds the well-structure region 104, between source 108 anddrain 110 regions of the microwire. The source and drain (S/D) regions108/110 are doped with a second dopant, opposite to the first dopant.For example, the first dopant may be n-type and the second dopantp-type. Alternately, the first dopant may be p-type and first dopantn-type. Thus, the microwire alternating highly and lightly dopedcylindrical regions are either an NPN or PNP sequence.

A gate dielectric ring 112 overlies the channel ring 106. Typically, thegate dielectric ring 112 has a ring thickness 114 in the range of 10 to60 nm. A gate electrode ring 116 overlies the gate dielectric ring 112.

FIGS. 2A and 2B are partial cross-sectional views of a first variationof the well-structure anti-punch-through microwire device of FIGS. 1Aand 1B. The microwire 102 has an outer shell wall 200, and the channelring 106 is formed external to the microwire outer shell wall 200.

Referencing any of the above-mentioned figures, the channel ring 106 isformed from an intrinsic or lightly doped silicon (Si) layer having adopant concentration of less than about 2×10¹⁶ per cubic centimeter(cm⁻³). In contrast, the well-structure region 104 has a first dopantconcentration of greater than about 5×10¹⁶ cm⁻³, underlying the channellayer 106. Whether the channel ring 106 is formed internal or externalto the microwire 102, the channel ring 106 has a ring thickness 202 inthe range of 30 to 90 nm.

In one aspect, the microwire 102 has a diameter 204 of greater than 500nanometers (nm). However, the above-described structure can also beenabled using smaller microwires having a diameter of greater than 50nm. The microwire 102 may also be referred to as a nanowire.

Functional Description

FIGS. 3 through 5 are partial cross-sectional views depicting steps inthe fabrication of a completed well-structure microwire device. Themicrowires are grown (e.g., for PMOS devices) with modulated doping thatdefines highly-doped P⁺ source and drain regions, and a moderately-dopedN⁻ “well” region that defines the device channel length. The N⁻ dopingcan be constantly on for the entire growth cycle, with the P⁺ dopingbeing turned on and off (see FIG. 6).

After microwire growth, the catalyst material is removed and anintrinsic Si shell is epitaxially grown on the surface of the microwire,see FIG. 3. The layer thickness can be precisely controlled, therebyallowing full depletion of the channel region when the device is turnedon. The intrinsic region can be oxidized using a variety of means,including wet or dry thermal oxidation, HDP oxidation, or depositing aCVD-based oxide. This oxide forms the gate insulator shell for thetransistor device.

FIG. 4 depicts the device of FIG. 3 after etching of the outer shells(gate material, gate insulator, and intrinsic epi-Si). The wire diameteris shown to be greater than 500 nm is this example.

FIG. 5 depicts the final device configuration with electrode contacts.The current path is indicated by dashed line. A PMOS device architectureis shown in this example. An NMOS device would require an N⁺-P⁻-N⁺doping profile. The highly doped P⁺ regions are contacted as the sourceand drain, while the intrinsic Si shell acts as the channel, and the N⁻region acts as an effective well between the source and drain (i.e., toprevent back-side conductance/leakage). The various shell layers can beetched using an end-in etch process. In particular, the outer shell gateelectrode can be etched using this scheme through the contact holes. Thechannel length is controlled by the length of the N⁻ well, as theintrinsic Si directly in contact with the P+ regions will likelyexperience some diffusion of dopant material during varioushigh-temperature processing steps (e.g., oxidation).

FIG. 6 is a diagram depicting a silicon microwire growth process using avapor-liquid-solid (VLS) approach. Catalyst balls 600 are formed on a111 Si substrate 602. N⁻-doped silane flows at appropriate growthconditions (temperature and pressure controlled) causing nucleation ofan intrinsic Si microwire. The nucleation step can also be accomplishedwith intrinsic Si, followed by the addition of the N− dopant gas for theremainder of the growth. P⁺ dopant gas is turned on, providingheavily-doped source/drain region 1. The P⁺ dopant is stopped, providinglightly-doped N⁻ “well” region. The P⁺ dopant is restarted forsource/drain region 2. After sufficient growth, all gases are stoppedand growth is terminated.

FIG. 7 is a diagram depicting a VLS Si microwire growth process using analternate doping technique. As shown, both the P⁺ and N⁻ are both pulsemodulated. In this example, the modulation is complementary, however, inother aspects not shown, there may be periods of overlap when both theP⁺ and N⁻ dopant flow, or when neither the P⁺ or N⁻ dopant flow.

Although a VLS process is described, it should be understood that themicrowires may be fabricated using other techniques, which may be moreoptimal for in-situ doping. The overall structure is independent of thegrowth process, provided that the Si material is effectively doped. ThisVLS process typically uses gold as a catalyst, but other materials suchas copper or aluminum have been reported as successful catalysts. ThickSi wires typically have a 111 axial orientation, and in order to ensuregood verticality normal to the substrate, 111-normal Si growth wafersmay be used. The catalyst can be deposited on the substrate either as acontinuous film that is heated and agglomerated to form discrete balls,deposited over a patterned oxide/shadow mask to control the placement ofthe agglomerated balls, or deposited as functionalized particles.

Following growth of the microwires, the catalyst balls are etched fromthe ends of the microwires, and the microwires are harvested from thesubstrate, through an reactive ion etch (RIE)-and-undercut process,sonication, or other means known in the art. The harvested microwiresare then put in suspension and deposited onto a largerhigh-temperature-incompatible substrate (e.g., glass, metal, or plastic)using, for example, dielectrophoresis. The growth process uses dopedsilane, doped disilane, or doped chlorosilanes (e.g., SiCl₄) for thesource material.

FIG. 8 depicts a conventional IC-based CMOS device on a bulk Sisubstrate (prior art). As shown in FIGS. 6 and 7, as the microwires aregrown, they are doped with alternating dopant concentrations andspecies, such that an example PMOS structure would have a heavily dopedP⁺ region (e.g., with boron as the dopant species), followed by an N⁻region (e.g., with a low concentration of phosphorous as the dopant),and then with another P⁺ region. The basic doped microwire structuremimics the PMOS device of FIG. 8, where the substrate is lightly dopedN⁻ and the source and drain regions are highly-doped P⁺.

FIG. 9 depicts steps in the fabrication of an in-situ-doped microwirestructure with shell layers of intrinsic Si, oxide, and conductive gate,based on a VLS-type growth process. The catalyst material 600 is formedon the substrate 602 and growth process is started (a). Dopant speciesare added during growth in such a way so as to have a sharp cut-offbetween the P⁺ N⁻ regions (b). The N⁻ dopant species can be left onduring the entire growth process (similar to a P⁺ implant for PMOSdevices fabricated on an N⁻ substrate), see FIG. 6. This process allowsfor an abrupt transition region between the two adjacent areas, withinthe limits imposed by the materials and growth processes themselves(e.g., depletion of dopant from the catalyst).

After growth is completed, the catalyst ball is removed from the end ofthe microwire (c). This removal can be accomplished using a wet etch,provided that care is taken to avoid causing the microwires to stick toone another during the drying step (e.g., by using acritical-point-dryer). Example etches for a Au catalyst that do notaffect the microwire itself might include HCl/HNO₃, KI/I₂, or NaCN.

Following catalyst removal, the wire is cleaned and an intrinsic Silayer is deposited over the surface of the wire to form a cylindricalshell (d). A perfect epitaxial silicon provides a defect-free materialfor the channel portion of the microwire device (see FIG. 2). Thethickness of the epitaxial Si layer should be sufficient to provide a 30to 90 nm-thick channel, and after thermal oxidation (e), a 10 to 60nm-thick gate insulator layer is formed. Depending on the conditionsused for the thermal oxidation, there might be significant dopantdiffusion from the as-grown microwire into the intrinsic epi-Si layer.The oxidation process conditions can be tailored so that diffusion fromthe lightly-doped well region is avoided. For example, a heavier dopantspecies such as As can be used that does not diffuse as readily aslighter elements. As another example, a low temperature high densityplasma (HDP) or wet oxidation process can be used to limit diffusion.After oxidation of the epi-Si layer, a final conductive gate shell isdeposited onto the microwire (f). The gate material can be anyconductive layer that has an appropriate work function for deviceoperation (e.g., P⁺ Si, WN, or TaAlN). After the final shell isdeposited, the wires are harvested and put into suspension with acompatible fluid.

Note: the microwire of FIGS. 1A and 1B may be made in a similar manner,except that the step (Step d) of forming an intrinsic Si layer isomitted.

FIG. 10 is a flowchart illustrating a method for the fabrication of awell-structure anti-punch-through microwire device. Although the methodis depicted as a sequence of numbered steps for clarity, the numberingdoes not necessarily dictate the order of the steps. It should beunderstood that some of these steps may be skipped, performed inparallel, or performed without the requirement of maintaining a strictorder of sequence. The method starts at Step 1000.

Step 1002 forms a microwire with alternating highly and lightly dopedcylindrical regions (e.g., PNP or NPN sequences). As noted above, themicrowire may have a diameter of greater than 500 nm, however the designis suitable for smaller nanowires (i.e. nanowires) having a diameter ofgreater than 50 nm. Step 1004 forms a channel ring surrounding a firstdopant well-structure region in the microwire, between source and drainregions of the microwire having a second dopant, opposite to the firstdopant. Step 1006 forms a gate dielectric ring surrounding the channelring. Step 1008 forms a gate electrode ring surrounding the gatedielectric ring. In one aspect, forming the microwire in Step 1002includes forming a microwire with an outer shell wall, and forming thechannel ring in Step 1004 includes forming a channel ring external tothe microwire outer shell wall.

Typically, the channel ring is formed from an intrinsic silicon layerhaving a dopant concentration of less than about 2×10¹⁶ per cubiccentimeter (cm⁻³), overlying a well-structure region having a firstdopant concentration of greater than about 5×10¹⁶ cm⁻³.

Regardless of whether the channel ring is formed internal or external tothe microwire, the channel typically has a ring thickness in the rangeof 30 to 90 nm. The gate dielectric ring typically has a ring thicknessin the range of 10 to 60 nm.

In one aspect, forming the microwire in Step 1002 includes substeps.Step 1002 a deposits a nucleation catalyst on a substrate to grow themicrowire. Step 1002 b introduces a silane precursor. Step 1002 cintroduces the first dopant, and Step 1002 d pulse modulates theintroduction of the second dopant. Alternately, Step 1002 c introducesthe second dopant and Step 1002 d pulse modulates the introduction ofthe first dopant. In another aspect, Step 1002 c pulse modulates theintroduction of the second dopant in a first modulation cycle, whileStep 1002 d pulse modulates the introduction of the first dopant in asecond modulation cycle. As shown in FIG. 7, the first and secondmodulation cycles may be complementary (opposite). Alternately, thecycles may overlap, or there may be gaps of no dopant introductionbetween cycles.

In another aspect, forming the channel ring surrounding the first dopantwell-structure region includes substeps. Subsequent to forming thenanowire, Step 1004 a removes the nucleation catalyst, and Step 1004 bepitaxially grows an intrinsic Si layer surrounding the microwire.

Forming the gate dielectric ring surrounding the channel ring in Step1006 may include forming an oxidized Si layer overlying the intrinsicSi. For example, wet thermal oxidation, dry thermal oxidation, or a highdensity plasma (HDP) process may be used to oxidize the intrinsic Si.Alternately, a chemical vapor deposition (CVD) process may be used todeposit oxidized Si overlying the intrinsic Si. Forming the gateelectrode ring surrounding the gate dielectric ring may includesubsteps. Step 1008 a deposits a gate electrode material overlying theoxidized intrinsic Si. Step 1008 b selectively etches the gate electrodematerial, oxidized intrinsic Si, and intrinsic Si layer surrounding thesource and drain regions.

A well-structure microwire transistor device has been provided. Examplesof particular structural details, dimensions, and processes have beenpresented to illustrate the invention. However, the invention is notlimited to merely these examples. Other variations and embodiments ofthe invention will occur to those skilled in the art.

I claim:
 1. A method for the fabrication of a well-structureanti-punch-through microwire device, the method comprising: forming amicrowire of lightly first doped cylindrical regions alternating withhighly second doped cylindrical regions, where the first dopant isselected from a group consisting of n and p-type dopants, and the firstdopant is opposite to the second dopant; forming a channel ringsurrounding a well-structure region in the microwire having the firstdopant, between source and drain regions of the microwire having thesecond dopant; forming a gate dielectric ring surrounding the channelring; and, forming a gate electrode ring surrounding the gate dielectricring.
 2. The method of claim 1 wherein forming the microwire includesforming a microwire with an outer shell wall; and, wherein forming thechannel ring includes forming a channel ring external to the microwireouter shell wall.
 3. The method of claim 1 wherein forming the channelring overlying the first dopant well-structure region in the microwireincludes forming an intrinsic silicon (Si) layer having a dopantconcentration of less than about 2×10¹⁶ per cubic centimeter (cm⁻³),overlying a well-structure region having a first dopant concentration ofgreater than about 5×10¹⁶ cm⁻³.
 4. The method of claim 1 wherein formingthe microwire includes forming a microwire having a diameter of greaterthan 500 nanometers (nm).
 5. The method of claim 1 wherein forming themicrowire includes forming a microwire having a diameter of greater than50 nm.
 6. The method of claim 1 wherein forming the channel ringoverlying the first dopant well-structure region in the microwireincludes forming a channel having a ring thickness in a range of 30 to90 nanometers (nm).
 7. The method of claim 1 wherein forming themicrowire includes: depositing a nucleation catalyst on a substrate togrow the microwire; introducing a silane precursor; introducing thefirst dopant; and, pulse modulating the introduction of the seconddopant.
 8. The method of claim 1 wherein forming the microwire includes:depositing a nucleation catalyst on a substrate; introducing a silaneprecursor; pulse modulating the introduction of the second dopant in afirst modulation cycle; and, pulse modulating the introduction of thefirst dopant in a second modulation cycle.
 9. The method of claim 1wherein forming the channel ring surrounding the first dopantwell-structure region in the microwire includes: subsequent to formingthe nanowire, removing a nucleation catalyst; and, epitaxially growingan intrinsic Si layer surrounding the microwire.
 10. The method of claim7 wherein forming the gate dielectric ring surrounding the channel ringincludes forming an oxidized Si layer overlying the intrinsic Si; andwherein forming the gate electrode ring surrounding the gate dielectricring includes: depositing a gate electrode material overlying theoxidized intrinsic Si; and, selectively etching the gate electrodematerial, oxidized intrinsic Si, and intrinsic Si layer surrounding thesource and drain regions.
 11. The method of claim 10 wherein forming theoxidized Si includes using a process selected from a group consisting ofwet thermal oxidation of the intrinsic Si, dry thermal oxidation of theintrinsic Si, high density plasma (HDP) oxidation of the intrinsic Si,and chemical vapor deposition (CVD) of the oxidized Si overlying theintrinsic Si.
 12. The method of claim 1 wherein forming the microwirewith alternating highly and lightly doped cylindrical regions includesforming a microwire with a doped cylindrical sequence selected from agroup consisting of NPN and PNP.
 13. The method of claim 1 whereinforming the gate dielectric ring overlying the channel ring includesforming a gate dielectric ring having a ring thickness in a range of 10to 60 nm.